EDN

DRAM controller throughput may be the next key to SoC performance

As SoC architects make the transition from CPU-centric designs with a single major processor to multiprocessing designs in which many processing peers carry on in parallel, efficient use of external ...
Design-Reuse

Sonics Combines DRAM Scheduler with Synopsys Protocol Controller For Integrated High-Performance Memory Subsystem

MemMax DRAM System Ensures Maximum Bandwidth Utilization in High-End SoCs MILPITAS, Calif. -- June 23, 2009-- Sonics, Inc. ®, a premier supplier of intelligent on-chip communications solutions has ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...