EDN

Avoid signal-integrity blowouts in SOC-design IP-block integration

Many small and large design teams use third-party IP (intellectual property) to accelerate SOC (system-on-chip) design by importing functional blocks, such as data converters, PLLs, Ethernet PHY ...
EDN

SoC/IP designs need next-gen solutions for integration verification

Today's multimillion-gate SoC designs consist of mixed intellectual property — CPU cores, memory, ADC/DAC and more — that represent multiple levels of design abstractions, such as RTL, gates, ...
Nasdaq

Cadence Advances Hyperscale SoC Design with Expanded IP Portfolio for TSMC N3E Process Featuring Next-Generation 224G-LR SerDes IP

Proven interface IP architectures realized significant gains in performance and power efficiency on the TSMC N3E process 224G-LR SerDes PHY IP on the TSMC N3E process has achieved first-pass silicon ...
Semiconductor Engineering

Streamlining SoC Design With Advanced IP And Integration Solutions

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The ...
Semiconductor Engineering

Why SoC Designers Need Purpose-Built Semiconductor IP Catalog Tools

Semiconductor intellectual property (IP) management, reuse, and change tracking are essential for efficiently creating chip designs based on proven building blocks, reducing your time-to-market, and ...
NBC News

HDL Design House Adopts Magma's Full Suite of Software to Accelerate SoC and IP Development

SAN JOSE, Calif., March 31, 2011 (GLOBE NEWSWIRE) -- Magma Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, and HDL Design House, creators of re-usable IP cores, verification ...
Seeking Alpha

Arteris Interconnect IP Selected by VeriSilicon for High-Performance SoC Design

CAMPBELL, Calif., Sept. 10, 2024 (GLOBE NEWSWIRE) -- Arteris, Inc. (AIP), a leading provider of system IP which accelerates system-on-chip (SoC) creation, today announced that VeriSilicon (688521.SH), ...
Electronic Design

Advanced SoC Development Uses Next-Gen IP Integration Tools

The considerable growth of the number of logical cores in a chip increases the number of networks-on-chip (NoCs) per system-on-chip (SoC), fueling design complexity. Demand is on the rise for better ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of the industry’s first Verification IP (VIP) and System-Level VIP (System VIP) for the ...
Business Wire

Cadence Accelerates Hyperscale SoC Design with Next-Generation 112G Extended Long-Reach SerDes IP on TSMC’s N4P Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s N4P process for hyperscale ASICs, artificial ...
Electronic Design

Schema Is Devised For SoC Design And IP Reuse

Wireless devices are truly embedded wonders. The embedded systems within handsets and other devices propel these devices toward a smaller, more feature-rich future. To the engineers working on ...
Embedded

Four key features every automotive SoC design needs

Vehicles can do much more than they were capable of a decade ago. Today’s modern connected vehicles have many convenient capabilities, from lane departure warnings to automated braking and ...