Semiconductor Engineering

Does Your RISC-V Core Meet The Standard?

Verifying an extensible processor is more than a one-step process, especially when software compatibility is important.
Semiconductor Engineering

Formal Verification Of RISC-V Cores

RISC-V is hot and stands at the beginning of what may be a major shift in the industry. Even a cursory review of upcoming conferences programs and recent technical articles makes that clear. While it ...
EDN

RISC-V’s CPU Verification Challenge

RISC-V is gaining attention throughout the semiconductor industry. It offers the lure of an open-source solution that anyone can leverage to create their own CPU or custom accelerator. Of course, dig ...
Business Insider

Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Complete range of tests for the entire RISC-V core verification stack from ISA to system-level interaction and performance Test Suite Synthesis AI Technology tracks complex, un-predictable bugs and ...
Dataquest

Breker and Frontgrade Gaisler ally on high-reliability RISC-V fault tolerant processor core

Breker Verification Systems has confirmed its RISC-V functional verification solutions were pivotal for verification of the NOEL-V, one of Frontgrade Gaisler’s fault-tolerant RISC-V processor IP cores ...
EDN

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

Developed with SiFive to address RISC-V system integration validation; generates high-impact SoC verification test suite with minimal manual effort. Breker Verification Systems, the leading provider ...
KELOLAND News

Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification

SAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed in more ...
Business Wire

Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator

ZURICH--(BUSINESS WIRE)--Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the collaboration with Metrics, working on the verification ...