Nasdaq

Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development

Arteris and Semidynamics partnership enhances the flexibility and highly configurable interoperability of RISC-V processor IP with system IP. Integrated and optimized solutions will focus on ...
Geeky Gadgets

RISC OS alternative operating system hits Kickstarter

A new Kickstarter project has launched this month, looking for backers to help build a power saving computer operating system and push RISC OS to more hardware platforms. German developer Stefan ...
TweakTown

RISC-V systems support replacing RAM sticks WITHOUT powering off the system

The upcoming version 6.11 of the mainline Linux kernel has support for RISC-V memory hot plugging, meaning you can pull RAM sticks out of your PC without turning it off... very nice. The Linux kernel ...

Milk-V Titan gives developers a plug-and-play RISC-V desktop

Unlike previous prototypes, which were limited to embedded or experimental use, the Titan targets mainstream usability. Its ...

Bolt wants to take on Nvidia by building a RISC-V graphics processor

Bolt Graphics wants to take on Nvidia and AMD by building a RISC-V graphics processor ...
EDN

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

Developed with SiFive to address RISC-V system integration validation; generates high-impact SoC verification test suite with minimal manual effort. Breker Verification Systems, the leading provider ...
The Next Platform

RISC-V In The Datacenter Is No Risky Proposition

It was only a matter of time, perhaps, but the skyrocketing costs of designing chips is colliding with the ever-increasing need for performance, price/performance, and performance per watt. Something ...
Semiconductor Engineering

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.)

A new technical paper titled “Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems” was published by researchers at Inha University, Intel Labs, Electronics and ...
Semiconductor Engineering

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao ...
The Next Platform

Strong Showing for First Experimental RISC-V Supercomputer

A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates a potential ...
TechNode

China’s chip industry is embracing RISC-V

Every Wednesday and Friday, TechNode’s Briefing newsletter delivers a roundup of the most important news in China tech, straight to your inbox. Sign up On June 21, Nuclei System Technology, a Shanghai ...