EDN

Calypto fields RTL-clock-gating tool

EDA start-up Calypto Inc has broadened its product portfolio beyond system-to-RTL (register-transfer-level) functional-verification tools with the introduction of an automated clock-gating tool for ...
EDN

Power analysis of clock gating at RTL

In today’s semiconductor designs, lower power consumption is mandatory for mobile and handheld applications for longer battery life and even networking or storage devices for low carbon footprint ...
Semiconductor Engineering

Clean Your Clock

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating … and ...
Semiconductor Engineering

Design Topology Requires Physical Data

To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and ...
Electronic Design

Implementing An Efficient RTL Clock Gating Analysis Flow

Lowering the power consumption of consumer products and networking centers is an important design consideration. The same goes for many of the processor cores that go into these devices. This paper ...