In a previous article, Getting started in structured assembly in complex SoC designs, an unexceptional system-on-chip (SoC) design was shown to contain hundreds of intellectual property (IP) blocks.

This isn't about memory chips, but implementable logic blocks for chip vendors, and it's a significant milestone for the ...

How can power be optimized across an entire chip when most of a chip’s content comes from third-party IP? Power is quickly becoming a major differentiator for products, regardless of whether they are ...

Is there a standard way to hook up specifically low-power IP blocks today? For all intents and purposes, no. Before even talking about IP interoperability in terms of power, Philippe Magarshack, ...

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual ...

Irvine, CA – July 19, 2005-- Onyx Semiconductor recently announced the availability of two jointly developed IP blocks for RF and power regulation functions. The OY5100 and OY6100 IP blocks have ...

A line of EtherNet/IP machine-mount I/O blocks and an IP 67 unmanaged switch have a low initial cost per point, says the vendor. Fast and easy IP addressing is accomplished using BOOTP/DHCP, through ...

If you want to use a display or camera with an FPGA, you will often end up with a MIPI-based solution. As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera ...