Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
EDN

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
EDN

Synopsys Improves Memory Interface IP Integration

Synopsys, Inc. today announced the immediate availability of the DesignWare® DDR PHY compiler, supporting DDR2, DDR3, LPDDR and LPDDR2 SDRAMs. “As a leading fabless design integrator, GUC is committed ...
Electronic Design

DDR3 and DDR2 Memory IP Bolsters SoC Designs

A full range of DesignWare DDR intellectual property (IP) is available for systems-on-a-chip (SoCs) that require an interface to high-performance DDR3, DDR2, and DDR memory subsystems. The DesignWare ...
Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Design-Reuse

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7, 2010 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced availability of the ...