EDN

DRAM controller throughput may be the next key to SoC performance

As SoC architects make the transition from CPU-centric designs with a single major processor to multiprocessing designs in which many processing peers carry on in parallel, efficient use of external ...
EDN

NEC adds L2 cache, DRAM controller to Vr processor

SANTA CLARA, Calif. — NEC Corp. has taken the wraps off a MIPS-based 64-bit embedded processor that integrates Level 2 cache and a DRAM controller, both equipped with error-correction coding features.