Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Design-Reuse

New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

DesignWare Universal DDR Protocol and Memory Controllers Feature a DFI 2.1-compliant Interface and Support for DDR2, DDR3, Mobile DDR and LPDDR2 Standards MOUNTAIN VIEW, Calif., April 28, 2010 -- ...
Design-Reuse

Uniquify Releases Industry's First Smart DDR Memory Controllers

The DDR2 and mobile DDR memory controllers from Santa Clara, Calif. based Uniquify, Inc. solve system level timing issues. Santa Clara, Calif. -- April 10, 2007-- Uniquify, Inc., the leading edge IP ...
EDN

DDR PHY interface spec to be released at Denali’s MemCon

SAN FRANCISCO — A DDR PHY Interface (DFI) specification, seeking to define a common interface between memory controller logic and the PHY interface, is set to be unveiled next week at an event hosted ...
Business Wire

Silicon Valley Startup Granted US Patent on Critical DDR2/DDR3 Timing Innovation for Chip Designs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Uniquify, a Silicon Valley semiconductor IP start-up (http://www.uniquify.com), today announced that it has been granted a ...
Yahoo Finance

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan, July 22, 2025--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, ...
Semiconductor Engineering

Advantages Of LPDDR5: A New Clocking Scheme

Innovative new clocking schemes in the latest LPDDR standard enable easier implementation of controllers and PHYs at maximum data rate as well as new options for power consumption. Earlier this year, ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...
Electronic Design

Achieve Reliability, Availability, And Serviceability For Memory Interfaces

The world is seeing explosive growth in the aggregation of new computing, storage, and computing infrastructure equipment into data centers. These systems are being used for cloud, e-commerce, and ...
Semiconductor Engineering

Advances In Power Management For Physical IP In 28nm And FinFET Process Nodes

Engineering techniques to reduce power consumption by lowering the supply voltage and slowing the clock speed have reached practical limits of the semiconductor technologies. Newer solutions, which ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...