Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a ...

Santa Cruz, Calif. — Designers frequently use clock gating to reduce IC power consumption, but it's hard to verify those changes in RTL code. A sequential equivalence checker from Calypto Design ...

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating … and ...

Well, summer has been and gone; and for most of us it was a time to relax and reflect on our working practices. What can we do to achieve better results? And what can we do to break out of the routine ...

Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been ...